View PD10018-166TQI_7634804.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? 1-800-379-4774 1 advance information rev. 00b 09/25/01 this document contains advance information data. issi reserves the right to make changes to its products at any time without n otice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2001, integrat ed silicon solution, inc. is61vpd51232 is61vpd51236 is61vpd10018 issi ? features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp and 119-pin pbga package single +2.5v, 5% operation auto power-down during deselect double cycle deselect snooze mode for reduced-power standby jtag boundary scan for pbga package description the issi is61vpd51232, is61vpd51236, and is61vpd10018 are high-speed, low-power synchronous static rams designed to provide burstable, high-performance memory for communication and networking applications. the is61vpd51232 is organized as 524,288 words by 32 bits and the is61vpd51236 is organized as 524,288 words by 36 bits. the is61vpd10018 is organized as 1,048,576 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge- triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ).input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. 512k x 32, 512k x 36, 1024k x 18 synchronous pipelined, double cycle deselect static ram advance information september 2001 fast access time symbol parameter -200 -166 units t kq clock access time 3.1 3.5 ns t kc cycle time 5 6 ns frequency 200 166 mhz
2 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? block diagram 19/20 binary counter bwa gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 17/18 19/20 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bwd ce ce2 ce2 bwb bwc 512kx32; 512kx36; 1024kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 4 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18)
integrated silicon solution, inc. ? 1-800-379-4774 3 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? pin configuration 100-pin tqfp 512k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output gnd ground gw synchronous global write enable mode burst sequence mode selection oe output enable v cc +2.5v power supply v ccq isolated output buffer supply: +2.5v zz snooze enable nc dqb dqb vccq gnd dqb dqb dqb dqb gnd vccq dqb dqb gnd nc vcc zz dqa dqa vccq gnd dqa dqa dqa dqa gnd vccq dqa dqa nc a a ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a a nc dqc dqc vccq gnd dqc dqc dqc dqc gnd vccq dqc dqc nc vcc nc gnd dqd dqd vccq gnd dqd dqd dqd dqd gnd vccq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vcc a a a a a a a a a 46 47 48 49 50
4 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? pin configuration a b c d e f g h j k l m n p r t u vccq nc nc dqc dqc vccq dqc dqc vccq dqd dqd vccq dqd dqd nc nc vccq a a a dqpc dqc dqc dqc dqc vcc dqd dqd dqd dqd dqpd a nc tms a a a gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode a tdi adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc a tck a a a gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd nc a tdo a a a dqpb dqb dqb dqb dqb vcc dqa dqa dqa dqa dqpa a nc nc vccq nc nc dqb dqb vccq dqb dqb vccq dqa dqa vccq dqa dqa nc zz vccq 1 2 3 4 5 6 7 dqpb dqb dqb vccq gnd dqb dqb dqb dqb gnd vccq dqb dqb gnd nc vcc zz dqa dqa vccq gnd dqa dqa dqa dqa gnd vccq dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a a dqpc dqc dqc vccq gnd dqc dqc dqc dqc gnd vccq dqc dqc nc vcc nc gnd dqd dqd vccq gnd dqd dqd dqd dqd gnd vccq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vcc a a a a a a a a a 46 47 48 49 50 512k x 36 119-pin pbga (top view) 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpd parity data input/output gnd ground gw synchronous global write enable mode burst sequence mode selection oe output enable tms, tdi, jtag boundary scan pins tck, tdo v cc +2.5v power supply v ccq isolated output buffer supply: +2.5v zz snooze enable
integrated silicon solution, inc. ? 1-800-379-4774 5 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? pin configuration a b c d e f g h j k l m n p r t u vccq nc nc dqb nc vccq nc dqb vccq nc dqb vccq dqb nc nc nc vccq a a a nc dqb nc dqb nc vcc dqb nc dqb nc dqpb a a tms a a a gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode a tdi adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc nc tck a a a gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd nc a tdo a a a dqpa nc dqa nc dqa vcc nc dqa nc dqa nc a a nc vccq nc nc nc dqa vccq dqa nc vccq dqa nc vccq nc dqa nc zz vccq 1 2 3 4 5 6 7 1024k x 18 119-pin pbga (top view) 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs adsc synchronous controller address status adsp synchronous processor address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable ce , ce2, ce2 synchronous chip enable clk synchronous clock dqa-dqd synchronous data input/output dqpa-dqpb parity data i/o; dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 gnd ground gw synchronous global write enable mode burst sequence mode selection oe output enable tms, tdi, jtag boundary scan pins tck, tdo v cc +2.5v power supply v ccq isolated output buffer supply: +2.5v zz snooze enable a nc nc vccq gnd nc dqpa dqa dqa gnd vccq dqa dqa gnd nc vcc zz dqa dqa vccq gnd dqa dqa nc nc gnd vccq nc nc nc a a ce ce2 nc nc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv a a nc nc nc vccq gnd nc nc dqb dqb gnd vccq dqb dqb nc vcc nc gnd dqb dqb vccq gnd dqb dqb dqpb nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vcc a a a a a a a a a 46 47 48 49 50
6 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? truth table (1-8) (3ce option) operation address ce ce2 ce2 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l xxxxl-hhigh-z deselect cycle, power-down none l h x l l xxxxl-hhigh-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none xxxhxxxxxx high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l xxxhl-hhigh-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst c urrent x x x l hhhhll-h q read cycle, suspend burst c urrent x x x l hhhhhl-hhigh-z read cycle, suspend burst c urrent h x x l x h h h l l-h q read cycle, suspend burst c urrent h x x l x hhhhl-hhigh-z write cycle, suspend burst c urrent x x x l h h h l x l-h d write cycle, suspend burst c urrent h x x l x h h l x l-h d note: 1. x means ? don ? t care. ? h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa , bwb , bwc or bwd ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqa ? s and dqpa. bwb enables writes to dqb ? s and dqpb. bwc enables writes to dqc ? s and dqpc. bwd enables writes to dqd ? s and dqpd. dqpa and dqpb are only available on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarification.
integrated silicon solution, inc. ? 1-800-379-4774 7 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? partial truth table function gw bwe bwa bwb bwc bwd read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx truth table (1-8) (1ce option) next cycle address ce adsp adsc adv write oe dq deselected none h x l x x x high-z read, begin external l l x x x l q read, begin external l l x x x h high-z write, begin external l h l x write x d read, begin external l h l x read l q read, begin external l h l x read h high-z read, burst next x h h l read l q read, burst next x h h l read h high-z read, burst next h x h l read l q read, burst next h x h l read h high-z write, burst next x h h l w rite x d write, burst next h x h l w rite x d read, suspend current x h h h read l q read, suspend current x h h h read h high-z read, suspend current h x h h read l q read, suspend current h x h h read h high-z write, suspend current x h h h w rite x d write, suspend current h x h h w rite x d note: 1. x means ? don ? t care. ? h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa , bwb , bwc or bwd ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqa ? s and dqpa. bwb enables writes to dqb ? s and dqpb. bwc enables writes to dqc ? s and dqpc. bwd enables writes to dqd ? s and dqpd. dqpa and dqpb are only available on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarification.
8 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? interleaved burst address table (mode = v cc or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) 0,0 1,0 0,1 a1', a0' = 1,1 absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias ? 40 to +85 c t stg storage temperature ? 55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ? 0.5 to v ccq + 0.5 v v in voltage relative to gnd for ? 0.5 to v cc + 0.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd ? 0.5 to 3.2 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
integrated silicon solution, inc. ? 1-800-379-4774 9 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? operating range range ambient temperature v cc v ccq commercial 0 c to +70 c 2.375 ? 2.625v 2.375 ? 2.625v industrial ? 40 c to +85 c 2.375 ? 2.625v 2.375 ? 2.625v dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ? 2.0 ma, v ccq = 2.5v 1.7 ? v v ol output low voltage i ol = 2.0 ma, v ccq = 2.5v ? 0.7 v v ih input high voltage v ccq = 2.5v 1.7 v ccq + 0.3 v v il input low voltage v ccq = 2.5v ? 0.3 0.7 v i li input leakage current gnd v in v ccq (2) com. ? 22a ind. ? 55 i lo output leakage current gnd v out v ccq , oe = v ih com. ? 22a ind. ? 55 power supply characteristics (over operating range) -200 -166 symbol parameter test conditions max. max. unit i cc ac operating device selected, com. 300 275 ma supply current all inputs = v il or v ih ind. 325 300 ma oe = v ih , vcc = max. cycle time t kc min. i sb standby current device deselected, com. 70 60 ma v cc = max., ind. 80 70 ma all inputs = v ih or v il clk cycle time t kc min. notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v cc . 2. the mode pin should be tied to vcc or gnd. it exhibits 10 a maximum leakage current when tied to - gnd + 0.2v or vcc ? 0.2v.
10 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing v ccq /2v and reference level output load see figures 1 and 2 ac test loads figure 2 1667 ? 5 pf including jig and scope 1538 ? output 2.5v figure 1 output buffer z o = 50 ? v ccq /2v 50 ?
integrated silicon solution, inc. ? 1-800-379-4774 11 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? read/write cycle switching characteristics (over operating range) -200 -166 symbol parameter min. max. min. max. unit f max clock frequency ? 200 ? 166 mhz t kc cycle time 5 ? 6 ? ns t kh clock high pulse width 2 ? 2.3 ? ns t kl clock low pulse width 2 ? 2.3 ? ns t kq clock access time ? 3.1 ? 3.5 ns t kqx (1) clock high to output invalid 1.0 ? 1.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z ? 3.1 ? 3.5 ns t oeq output enable to output valid ? 3.1 ? 3.5 ns t oelz (1,2) output enable to output low-z 0 ? 0 ? ns t oehz (1,2) output enable to output high-z ? 3.0 ? 3.2 ns t as address setup time 1.5 ? 1.5 ? ns t ss address status setup time 1.5 ? 1.5 ? ns t ws write setup time 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
12 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
integrated silicon solution, inc. ? 1-800-379-4774 13 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? write cycle switching characteristics (over operating range) -200 -166 symbol parameter min. max. min. max. unit t kc cycle time 5 ? 6 ? ns t kh clock high pulse width 2 ? 2.3 ? ns t kl clock low pulse width 2 ? 2.3 ? ns t as address setup time 1.5 ? 1.5 ? ns t ss address status setup time 1.5 ? 1.5 ? ns t ws write setup time 1.5 ? 1.5 ? ns t ds data in setup time 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? ns t ah address hold time 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? ns t dh data in hold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? ns
14 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? write cycle timing single write data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2a 2b
integrated silicon solution, inc. ? 1-800-379-4774 15 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z snooze mode electrical characteristics symbol parameter conditions min. max. unit i sb 2 current during snooze mode zz vih ? 15 ma t pds zz active to input ignored ? 2 cycle t pus zz inactive to input sampled 2 ? cycle t zzi zz active to snooze current ? 2 cycle t rzzi zz inactive to exit snooze current 0 ? ns
16 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? ieee 1149.1 serial boundary scan (jtag) the is61vf51236 and is61vf10018 have a serial bound- ary scan test access port (tap) in the pbga package only. (not available in tqfp package or with the is61vf51232.) this port operates in accordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (gnd) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v cc through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram
integrated silicon solution, inc. ? 1-800-379-4774 17 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v cc ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (gnd) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identification register definitions table. scan register sizes register name bit size ( x18) bit size (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 51 70 identification register definitions instruction field description 512k x 36 1m x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defines depth of sram. 512k or 1m 00111 01000 device width (22:18) defines with of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identification of sram vendor. 00011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1
18 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructi ons are listed as reserved and should not be used and the other five instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buffers. the sram does not implement the 1149.1 com- mands extest or intest or the preload portion of sample/preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instructions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not imple- mented, so the tap controller is not fully 1149.1 compli- ant. when the sample/preload instruction is loaded to the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock operates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/ preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk and clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
integrated silicon solution, inc. ? 1-800-379-4774 19 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram
20 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? tap electrical characteristics over the operating range (1,2) symbol parameter test conditions min. max. units v oh1 output high voltage i oh = ? 2.0 ma 1.7 ? v v oh2 output high voltage i oh = ? 100 ma 2.1 ? v v ol1 output low voltage i ol = 2.0 ma ? 0.7 v v ol2 output low voltage i ol = 100 ma ? 0.2 v v ih input high voltage 1.7 v cc +0.3 v v il input low voltage i olt = 2ma ? 0.3 0.7 v i x input load current gnd v i v ddq ? 55ma notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot:v il (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ac electrical characteristics (1) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ? ns f tf tck clock frequency ? 10 mhz t th tck clock high 40 ? ns t tl tck clock low 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t cs capture setup to tck rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns t tdov tck low to tdo valid ? 20 ns t tdox tck low to tdo invalid 0 ? ns notes: notes: notes: notes: notes: 7. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 8. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
integrated silicon solution, inc. ? 1-800-379-4774 21 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? don't care undefined tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx 1 2 3 4 5 6 t tlox t tlov tap timing 20 pf tdo gnd 50 ? 1.25v z 0 = 50 ? tap output load equivalent tap output load equivalent tap output load equivalent tap output load equivalent tap output load equivalent tap ac test conditions input pulse levels 0 to 2.5v input rise and fall times 1ns input timing reference levels 1.25v output reference levels 1.25v test load termination supply voltage 1.25v
22 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? boundary scan order (512k x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 19 dqb 7g 37 bwa 5l 55 dqd 2k 2 a 3t 20 dqb 6f 38 bwb 5g 56 dqd 1l 3 a 4t 21 dqb 7e 39 bwc 3g 57 dqd 2m 4 a 5t 22 dqb 7d 40 bwd 3l 58 dqd 1n 5 a 6r 23 dqb 7h 41 a 2b 59 dqd 1p 6 a 3b 24 dqb 6g 42 ce 4e 60 dqd 1k 7 a 5b 25 dqb 6e 43 a 3a 61 dqd 2l 8 dqa 6p 26 dqb 6d 44 a 2a 62 dqd 2n 9 dqa 7n 27 a 6a 45 dqc 2d 63 dqd 2p 10 dqa 6m 28 a 5a 46 dqc 1e 64 mode 3r 11 dqa 7l 29 adv 4g 47 dqc 2f 65 a 2c 12 dqa 6k 30 adsp 4a 48 dqc 1g 66 a 3c 13 dqa 7p 31 adsc 4b 49 dqc 2h 67 a 5c 14 dqa 6n 32 oe 4f 50 dqc 1d 68 a 6c 15 dqa 6l 33 bwe 4m 51 dqc 2e 69 a1 4n 16 dqa 7k 34 gw 4h 52 dqc 2g 70 a0 4p 17 zz 7t 35 clk 4k 53 dqc 1h 18 dqb 6h 36 a 6b 54 nc 5r boundary scan order (1m x 18) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 a 2r 14 dqa 7g 27 clk 4k 40 dqb 2k 2 a 2t 15 dqa 6f 27 a 6b 41 dqb 1l 3 a 3t 16 dqa 7e 29 bwa 5l 42 dqb 2m 4 a 5t 17 dqa 6d 30 bwb 3g 43 dqb 1n 5 a 6r 18 a 6t 31 a 2b 44 dqb 2p 6 a 3b 19 a 6a 32 ce 4e 45 mode 3r 7 a 5b 20 a 5a 33 a 3a 46 a 2c 8 dqa 7p 21 adv 4g 34 a 2a 47 a 3c 9 dqa 6n 22 adsp 4a 35 dqb 1d 48 a 5c 10 dqa 6l 23 adsc 4b 36 dqb 2e 49 a 6c 11 dqa 7k 24 oe 4f 37 dqb 2g 50 a1 4n 12 zz 7t 25 bwe 4m 38 dqb 1h 51 a0 4p 13 dqa 6h 26 gw 4h 39 nc 5r
integrated silicon solution, inc. ? 1-800-379-4774 23 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? ordering information commercial range: 0 c to +70 c speed order part number package 200 mhz is61vpd51232-200tq tqfp 166 mhz is61vpd51232-166tq tqfp industrial range: ? 40 c to +85 c speed order part number package 200 mhz is61vpd51232-200tqi tqfp 166 mhz is61vpd51232-166tqi tqfp commercial range: 0 c to +70 c speed order part number package 200 mhz is61vpd51236-200tq tqfp is61vpd51236-200b pbga 166 mhz is61vpd51236-166tq tqfp is61vpd51236-166b pbga industrial range: ? 40 c to +85 c speed order part number package 200 mhz is61vpd51236-200tqi tqfp is61vpd51236-200bi pbga 166 mhz is61vpd51236-166tqi tqfp is61vpd51236-166bi pbga
24 integrated silicon solution, inc. ? 1-800-379-4774 advance information rev. 00b 09/25/01 is61vpd51232 is61vpd51236 is61vpd10018 issi ? issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to +70 c speed order part number package 200 mhz is61vpd10018-200tq tqfp is61vpd10018-200b pbga 166 mhz is61vpd10018-166tq tqfp is61vpd10018-166b pbga industrial range: ? 40 c to +85 c speed order part number package 200 mhz is61vpd10018-200tqi tqfp is61vpd10018-200bi pbga 166 mhz is61vPD10018-166TQI tqfp is61vpd10018-166bi pbga

▲Up To Search▲

Price & Availability of PD10018-166TQI

	To Download PD10018-166TQI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .